There is a continuing desire to make integrated circuits increasingly smaller. One of the obstacles in developing smaller integrated circuits is due to the fact that the I/O pitch of printed circuit boards is typically far larger than the I/O pitch for electronic packages that are commonly mounted in the printed circuit boards.
This gap in I/O pitch between different electronic components is mainly addressed using fan-out approaches. As an example, a two-dimensional plane (e.g., a ball grid array) is commonly used for second level (i.e., electronic package to printed circuit board) interconnects. Therefore, conventional package architectures often have relatively larger footprints and higher cost to functionality ratios.
There is also a continuing need to reduce the z-height of electronic assemblies that include electronic packages mounted to printed circuit boards. Reducing the z-height of these types of electronic assemblies allows such electronic assemblies to be more readily incorporated into various small-scale electronic devices (e.g., mobile devices and/or wearables).